Design-Reuse

Domino Logic in ASIC Design Flow - Detailed Methodology and Breakthroughs in High Speed Design Automation Approach

Geneva -- September 22,2008 - Engineers at STMicroelectronic have revealed how to use domino logic, a very fast circuit design style utilized in the highest performance custom designs,in an automated ...
EDN

Monterey adds Synplicity synthesis to ASIC design flow

SAN MATEO, Calif. — Claiming to have a full RTL-to-GDSII design flow at last, Monterey Design Systems has added logic synthesis to its Dolphin placement and routing system. The Dolphin-RTL synthesis ...
Design-Reuse

Faraday Adopts Incentia for ASIC Synthesis & Timing Flow

Runtime speed and capacity of Incentia’s logic, test and low power synthesis & timing software crucial for high-performance, complex design success HSINCHU, Taiwan, and SANTA CLARA, Calif. – June ...
EDN

Synplicity fields ASIC DSP synthesis

Although Synplicity Inc. left the ASIC synthesis market last year, the company is targeting ASIC designers once again with a new edition of its Synplify DSP product. This time, however, the focus is ...
mccormick.northwestern.edu

COMP_ENG 459: VLSI Algorithmics

Introduction to advanced topics in synthesis and modeling of complex VLSI systems at behavioral and logic level. Topics include resource allocation, resource binding, scheduling, and controller design ...
Semiconductor Engineering

Why Your FPGA Synthesis Flow Requires Verification

When you think about it, logic synthesis is a vital but rather intimidating part of modern chip design. This process takes a high-level description of intended functionality, written in an RTL ...
mccormick.northwestern.edu

COMP_ENG 459: VLSI Algorithmics

Introduction to advanced topics in synthesis and modeling of complex VLSI systems at behavioral and logic level. Topics include resource allocation, resource binding, scheduling, and controller design ...