EDN

Timing Diagram Editors Simplify FPGA Synthesis

SynaptiCAD has released an updated version of its timing diagram editor family that simplifies creating the Synopsys Design Constraint (SDC) files used to define the ...
Design-Reuse

FPGA prototyping of complex SoCs: Partitioning and Timing Closure Challenges with Solutions

In the nanometer era, complex SoCs have higher risk of re-spins. Undoubtedly FPGA prototyping is the right way of pre-silicon SoC validation, accelerate system software development and to meet time-to ...
EDN

Building an FPGA FIFO without using logic resources

Today, FPGA designers are using these flexible devices to perform everything from simple glue logic tasks to implementing complicated system on a chip (SoC) functions. The efficiency and ease of ...
Business Wire

Open Source FPGA Launches Foundation to Accelerate Widespread Adoption of Programmable Logic

SALT LAKE CITY--(BUSINESS WIRE)--The Open Source FPGA Foundation today announces its formation as a nonprofit organization focused on accelerating worldwide awareness and widespread adoption of open ...
Electronic Design

Compact 16-nm FPGA Loads Up on Programmable Logic

The flagship offering in Lattice’s Avant-E family fits 500,000 logic units into a 15- x 13-mm package. Lattice Semiconductor’s new Avant architecture is purpose-built to extend the company’s focus on ...
Design-Reuse

A Reconfigurable System featuring Dynamically Extensible Embedded Microprocessor, FPGA and Customisable I/O

A system-chip targeting image and voice processing and recognition application domains is implemented as a representative of the potential of using programmable logic in system design. It features an ...
Electronic Design

Secure FPGA RISC-V SoC Forgoes Heatsink

How a cool FPGA needs so little power. The importance of a smaller RISC-V SoC FPGA. What the PolarFire SoC means to RISC-V developers. Why security and reliability are key to PolarFire’s success. Very ...